The present invention relates generally to Schottky barrier focal plane arrays, and more particularly, to Schottky barrier focal plane arrays having charge skimming and variable integration time, and methods of achieving such charge skimming and variable integration time.
Platinum silicide (PtSi) on P-silicon Schottky-barrier diodes have been proposed since 1973 for detecting infrared (IR) radiation, and large two-dimensional focal plane arrays are routinely fabricated in this technology. Schottky-barrier diodes are described in a paper by F. D. Shepherd et at. entitled "Silicon Schottky retinas for infrared imaging" in IEDM Tech. Dig., 1973, pp. 310-313, and a paper by F. D. Shepherd entitled "Recent advances in platinum silicide infrared focal plane arrays." in IEDM Tech. Dig., 1984, pp. 370-373. Fabrication of such devices is described in papers by W. F. Kosonocky et al. entitled "160.times.244-element PtSi Schottky barrier IR-CCD image sensor" in IEEE Trans. Electron Devices, vol. ED-32, pp. 1564-1573, 1985; M. Kimata et al. entitled "A 512.times.512-element PtSi Schottky-barrier infrared image sensor" in IEEE J. Solid-State Circuits, vol. SC-22, pp. 1124-1129, 1989; H. Elabd et al. entitled "488.times.512- and 244.times.256-element monolithic PtSi Schottky IR focal plane arrays." in Proc. SPIE, vol. 1107, 1989; E. T. Nelson et al. entitled "Wide field of view PtSi infrared focal plane array" Proc. SPIE, vol. 1308pp. 36-44, 1990; and M. J. McNutt, et al. entitled "Schottky-barrier infrared focal plane arrays with novel readout structures," IEEE J. Solid-State Circuits, vol. 25, pp. 602-608, 1990.
At the same time, the use of back-side illumination and a front-side reflecting cavity have improved diode quantum efficiency to the point where temperature resolution better than 0.1.degree. K. is achieved as is described by H. Elabd et al. in "Theory and measurements of photoresponse for thin film PdSi and PtSi infrared Schottky-barrier detectors with optical cavity." in RCA Rev., vol. 43. pp. 569-589, 1982. Recently, iridium silicide has been proposed for extended wavelength sensitivity, and large arrays have been demonstrated in the long-wave infrared spectrum. These are discussed in papers by P. W. Pellegrini, et al. entitled "IrSi Schottky-barrier diodes for infrared detection" in IEDM Tech. Dig., 1982, pp. 157-160, B.-Y. Tsaur et al. entitled "IrSi Schottky-barrier infrared detectors with 10 .mu.m cutoff wavelength" in IEEE Electron Device Lett., vol. 9, pp. 650-653, 1988, and B.-Y. Tsaur et al. entitled "128.times.128-element IrSi Schottky-barrier focal plane arrays for long-wavelength infrared imaging" in IEEE Electron Device Lett., vol. 10, pp. 361-363, 1989.
Nevertheless, the relatively low quantum efficiency of Schottky-barrier diodes places a premium on relative diode area or fill factor. The reflecting plate may be dc biased as a field plate to control dime edge leakage as is described in a paper by M. J. McNutt entitled "Edge-leakage control in platinum silicide Schottky-barrier diodes used for infrared detection" in IEEE Electron Device Lett., vol. 9, pp. 394-396, 1988, and in U.S. Pat. No. 4,857,979 entitled "Platinum Silicide Imager" issued to M. J. McNutt. This eliminates the N guard-ring structure commonly used for leakage suppression as is discussed in some of the above references, and increases the focal plane array area available for the sensor diode. The increased fill factor captures more photons and improves the focal plane array sensitivity.
The provision of variable integration time provides an electronic shutter function that is a desirable addition to any focal plane array. However, it normally requires a common gate and drain adjacent to each sensor diode to drain off charge such that the diode potential is pinned and signal charge integration is temporarily suppressed. This has the disadvantage of using chip area that could be allocated to the diode, thus reducing fill factor. Another conventional approach is discussed in a paper by K. Konuma et al. entitled "324.times.487 Schottky-barrier infrared imager" in IEEE Trans. Electron Devices, vol. 37, pp. 629-635, 1990, in which the device sweeps out excess charge through a separate readout cycle, but this requires higher clock frequencies and limits the range over which the integration time can be varied. The normal readout and the charge sweep-out functions have to be compressed into the time otherwise allowed for readout only.
U.S. Pat. No. 4,866,496 issued to Audier discloses a charge skimming function that is similar in concept to that of the present invention. However, the charge skimming of the Audier patent is achieved through the use of multiple additional gates that partition the signal charge into a part that is saved and a part that is discarded. This circuit is predominantly aimed at mercury-cadmium-telluride detectors. However, besides providing the additional function of variable integration time, the present invention eliminates the need for the additional gate circuitry that is required by Audier. The efficient use of space is critical in monolithic focal plane arrays (e.g. Schottky barrier arrays).
U.S. Pat. No. 4,896,340 issued to Caro describes a general scheme for the partial input of signal charge into a charge coupled device. This patent is directed to hybrid mercury-cadmium-telluride focal plane arrays which have specific input requirements for biasing the diode and handling the large current. The Caro patent is similar to Audier in that it eliminates part of the signal charge, thus having a function similar to the present charge skimming function, but the implementation requires additional circuitry on the chip and is quite different in its execution.
U.S. Pat. No. 4,994,876 issued to Hiss describes a three dimensional storage structure that is used to increase the storage capacity of a readout circuit. This patent discloses increasing the mount or charge that can be handled, and is also aimed at hybrid mercury-cadmium-telluride arrays.
U.S. Pat. No. 5,003,565 issued to Yoshida describes a method for supplying individual control voltages to charge skimming circuits at each sensor site in the array. This is useful for eliminating the differences in diode sensitivity. This charge skimming technique is commonly used in the art. The present invention is not directed at tuning the charge skimming at each diode, and the thrust of the present invention is toward eliminating the charge skimming apparatus that is used in the Yoshida patent and elsewhere.
Accordingly, it is an objective of the present invention to provide for a focal plane array, and more particularly a Schottky-barrier diode focal plane array, having charge skimming and variable integration time that does not require additional readout circuit structure as is required in conventional circuit designs, and to methods for providing charge skimming and variable integration time in Schottky-barrier diode focal plane arrays.